1. Technical Field of the Invention
The present invention relates to an improved differential receiver.
2. Description of Related Art
Techniques have been developed for facilitating high-speed electrical communication over buses. High-speed communication uses low voltage swing signals that require a differential signaling technique.
To support differential signaling in integrated circuits (IC's), the circuit is designed to convert internal full swing signals to external low voltage differential signals and external low voltage differential signals to core acceptable signals. Generally differential receivers are used to accept external low voltage swing differential signals, but some noise is induced in the differential receivers at the time of reception that leads to power dissipation in the circuit.
FIG. 1 shows a circuit schematic of a conventional differential receiver circuit used in differential signaling applications. In FIG. 1, N11 and N12 are input NMOS transistors having their gates connected to differential input pads PAD and PADbar. PMOSs P11 and P12 are load transistors. NMOSs N13 and N14 and resistor R11 form a current sink.
The operation the differential amplifier is not explained herein. Details of one such differential amplifier is explained in book “CMOS Circuit Design, Layout and Simulations” by R. Jacob Baker, Harry W. Li and David E. Boyce.
In the schematic, reference 100 is not a part of the differential receiver, but represents an electrical parasitic appearing between I/O pads and I/O pins due to packaging. RT is a terminating resistor placed outside the device. It is shown here just for reference.
To get a good high-speed performance, the differential receiver shown is generally provided with high current, high gain and high bandwidth. But such a receiver will introduce propagation of noise and glitches because the receiver is so fast that even a small and short time disturbance at the input is amplified and presented at the output. So the main problem with the differential receiver shown is its noise susceptibility.
The majority of the noise problem comes at the time of transition of differential signals. As the operating frequencies of digital electronic devices increases, the signal lines used to route signals between components begin to behave like transmission lines because of the faster edge rates of the signals. If the impedance of the transmission line and the receiver are not matched, a portion of the incoming signal is reflected back. Reflections cause distortion in the received signal, which may lead to false interpretation of the logical value of the incoming signal.
In case of differential input signals, as the transitions are in opposite direction, noise due to reflections is also in opposite directions. That is, if one line of the differential pair is having a noise overshoot, the other line will have an undershoot at the same time. So, in this case noise on the differential pair is differential in nature instead of common mode noise. If sufficiently large, this differential noise is easily accepted by the differential receiver.
FIG. 2 shows HSpice post-layout simulation results of the prior art receiver in FIG. 1 with package parasitic 100 (package stub). (Here parameters of package parasitic are considered for typical BGA package with L=4.5 nH, R=0.45 ohm, C=1.45 pf). In FIG. 2, IN and INbar are the differential input signals applied having time period of 4 ns and signal swing of 0.4V. PAD and PADbar are the actual input waveforms looked by the differential receiver. OUT1 is the output of the differential receiver. It can be seen that the noise is differential in nature instead of being common mode and because of this, there are glitches on output signal OUT1.
A resistive “termination” technique is often applied to reduce signal reflections. One of the resistive “termination” techniques used for differential signals is shown in FIG. 1. Here a terminating resistor RT is placed external to the IC, between the differential lines. But the external termination does not take into consideration the package stub 100. The package stub 100 may cause the external input signals IN/INbar to ring and thus the actual input signal looked by the receiver at nodes PAD/PADbar is distorted.
FIG. 3 shows the simulation results of FIG. 1, with noisy input at PAD and PAD bar. Output OUT1 shows a glitch, due to the noise at the input of receiver.
One solution to this can be provided by using on-chip termination instead of external termination. Here termination resistor RT is provided between PAD and PADbar. Signal quality is improved by the on-chip resistor due to removal of the ‘package stub’ 100. But on-chip termination would be undesirable in multi-point and multi-drop configurations of data transmission.
A second solution is adding a Schmitt trigger at the input thus introducing DC hysteresis. To add hysteresis characteristics in input receivers, the ranges of low and high level input voltages are changed depending upon the direction of transition in the input signal. Generally adding hysteresis increase the receiver delays and therefore degrades the performance in high-speed I/O operations.
FIG. 4 shows a prior art differential receiver with hysteresis as suggested in U.S. Pat. No: 5,796,281. The architecture of the receiver of FIG. 4 is the same as that of FIG. 1 except that NMOS N3 is used to provide hysteresis. The gate of N3 is connected to the output OUT1. Here the sizes of N11 and N12 are not same. Resistance offered by N11 in parallel with N3 (when OUT1 is at logic high, means N3 is on) should be equal to the resistance offered by N12. So the size of N11 is smaller than that of N12. When IN1=0, IN2=1, OUT1=0, transistor N3 is off. When IN1 rises from 0 to 1 and IN2 falls from 1 to 0, current starts flowing through N11, and hence through P11, which mirrors same current to P12. Current flowing through P12 charges the load at OUT1. Since the size of N11 in FIG. 4 is smaller than the size of N11 in FIG. 1, it reduces the charging current of the load, hence increase the rising delay.
When IN1=1, IN2=0, OUT1=1, transistor N3 is on. When IN1 falls from 1 to 0, conduction of N11 decreases and conduction of N12 increases. Load at OUT1 discharges through N12. In FIG. 1, when IN1 starts falling from 1 to 0, voltage at net1 increases, hence turns P12 off. But in FIG. 4, an increment in voltage level of net1 is slower because of the transistor N3 that is on. So the discharging of load at OUT1 will be slower as compared to the case of FIG. 1.
FIGURES and 6 show the dc analysis and transient analysis results of FIG. 4 that depict an increase in the propagation delay of the receiver of the prior art.
So, the receiver with hysteresis increases the noise immunity but sufficiently increases the delays, which restricts the high frequency operation of receiver.
Therefore, there is a need for a circuit with improved noise protection for differential signaling applications as in a differential receiver, while providing minimized power dissipation.